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Sheet目录3873

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PIC16F62X

DS40300C-page 50

Preliminary

2003 Microchip Technology Inc.

8.0

TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a

postscaler. It can be used as the PWM time-base for

PWM mode of the CCP module. The TMR2 register is

readable and writable, and is cleared on any device

RESET.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4

1:16,

selected

control

bits

T2CKPS1:T2CKPS0 (T2CON<1:0>).

The Timer2 module has an 8-bit Period Register PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon RESET.

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

Timer2 can be shut off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

8.1

Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

A write to the TMR2 register

A write to the T2CON register

Any device RESET (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset)

TMR2 is not cleared when T2CON is written.

8.2

Output of TMR2

The output of TMR2 (before the postscaler) is fed to the

Synchronous Serial Port module which optionally uses

it to generate shift clock.

FIGURE 8-1:

TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets flag

TMR2 reg

output (1)

RESET

Postscaler

Prescaler

PR2 reg

OSC/4

1:1

1:16

1:1, 1:4, 1:16

bit TMR2IF

Note

1: TMR2 register output can be software selected by the

SSP Module as a baud clock.

T2CKPS<1:0>

TOUTPS<3:0>

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